1. Field of the Invention
The invention pertains to a fast acquisition Clock Data Recovery (CDR) circuit for use in a communications system that does not transmit a clock signal separately from the data. The invention is particularly adapted for use in DWDM optical communication systems in which the data may be transmitted at various clock rates.
2. Description of the Related Technology
High-speed communications networks have become the backbone of the information industry. Due to constant technological improvements, data rates and capacities of these networks have grown rapidly in recent years and will continue to do so for the foreseeable future. Telecommunications services such as the Internet, wide area networks (WAN) and local area networks (LAN) are rapidly expanding. The related terminal equipment and transmission equipment have to be added to and/or replaced frequently to accommodate expansion and technological advances. Such replacement is expensive and becomes even more so when the new equipment has to operate compatibly with other older equipment which is still in the network. This requirement for compatibility between different generations of communications technology must be satisfied if the benefits of technological progress are to be fully realized.
Digital communications require not only the data itself but also a clock, so that the receiving station can synchronize on that data. It is possible to transmit the clock and the data separately on separate channels, but this is prohibitively expensive for long-distance communications, so other solutions have been found to achieve synchronization at the receiver. Most older communications devices can handle only one data rate, making synchronization relatively simple. But these have to be replaced by new equipment if the system is upgraded to a new data rate signal or even the same data rate but with a different format. These devices are impractical in systems that have a variable data rate requirement.
Some current communications receivers operate with an independent system clock, which must operate at several times the speed of the data. Thus the data rate is only a fraction of the rate which the components are capable of handling. These systems either operate on rather low data rates or require expensive working components that are capable of handling the high clock speeds necessary to handle high data rates.
A number of techniques have been developed to avoid these problems. One is to embed the clock signal in the data so that it can be extracted by the receiver. However, this requires devoting a portion of the bandwidth to clock content rather than data content, which can unnecessarily limit the data throughput.
Other methods have been found to artificially create a clock at the receiving end based on the signal transitions between data bits. This works well with data signal conventions which provide a transition with every bit, but becomes more complicated for transmission conventions that don't have a transition associated with every bit. An example of the latter is the Non-Return-to-Zero (NRZ) standard. Under this standard, a `1` bit can be represented by a binary transition (from high-to-low or low-to-high), while a `0` bit can be represented by no transition. The use of this standard has a number of advantages, but makes it more difficult to extract a clock signal from the transmitted data. For example, transmitting ten consecutive zero bits would result in no signal transitions for ten consecutive clock cycles, so the receiving circuit must `remember` the correct clock frequency for some period of time to avoid losing synchronization. There are also no transitions during the `dead` time between transmissions. After such a period of no data, when synchronization has been lost, the receiver must be able to quickly determine the correct clock frequency of a new transmission, or `lock` onto the data, from the irregularly spaced series of transitions. Thus, such a circuit has two primary requirements: 1) it must rapidly synchronize on a new data rate, 2) it must not excessively drift away from the existing data rate when a series of non-transitions occurs in the data signal.
Data circuits have been developed for the specific purpose of reconstructing a clock signal from such data streams, based on the data signal transitions. They are generally known under the generic term "Clock timing and Data Recovery" (CDR) circuits. For NRZ data, these circuits examine the existing transitions in the input data, artificially generate a clock based generally on these transitions, and maintain this clock during those periods of no transitions. To maintain an accurate clock during a period of no transitions (i.e., a series of `0` bits in the data), any change in clock speed must be kept at an acceptably low level. But synchronizing on a new data rate requires the clock speed to change quickly, thus creating a conflict between quickly determining the clock and accurately maintaining clock.
For low data rates, these problems might be solved fairly simply by incorporating a microprocessor-based algorithm that analyzed the transitions. But modern high-speed communications systems can operate at speeds of several hundred megahertz (MHz) up to several gigahertz (GHz), which is many times faster than even the fastest microprocessors could directly analyze. To perform clock signal reconstruction on such high-speed data, conventional receivers usually employ a bandpass filter or some device operating-like a bandpass filter such as a phase lock loop (PLL), with the operation frequency (central frequency) very close to the input signal frequency (data rate) in the CDR. For efficiently extracting the clock information, the filter has to have a very narrow bandpass (i.e., a very high Q-value). On the other hand, if the CDR is to operate on some frequency range (such as 10% of the central frequency), and to pick up (or lock on) the clock information easily, the Q-value should be lower. Obviously, there is a tradeoff in the requirements for these filters. A high Q-value allows faster detections of the correct clock speed, while a lower Q-value allows a wider range of clock speeds to be detected. Thus, conventional CDRs have been very limited for use in communications systems with potentially changeable data rates, or for products intended to serve a wide range of data rate needs. The problem is exacerbated in dense wavelength division multiplexed (DWDM) optical transmission systems used in local area and wide area networks and the like, in which data from multiple users and multiple equipment types is to be transmitted at different data rates over a common optical fiber link, and it is desired to use a recovered clock signal to condition each signal prior to and/or after transmission over the shared link, to thereby minimize the effects of interference with other signals being transmitted over that same fiber.
The popular data transmission convention referred to as Non-Return-to-Zero (NRZ) has no clock in its signal spectrum. This format generates a binary signal transition from one binary state to the other (either high-to-low or low-to-high) to represent a `1` bit and produces no transition to represent a `0` bit. The opposite association can also be used, with a `0` represented by a transition and a `1` by no transition. In either case, non-linear circuit operations are used to reproduce a clock signal from the data waveform, which must be filtered and processed because there are many clock transitions that do not appear in the data waveform. In conventional CDR circuits, a narrow bandpass filter is used for extracting the clock information. The filter "builds" the clock energy and, if its band width is narrow enough relative to data speed, its "inertia," also known as its Q, will generate clock signals even when transitions are absent. As a rule of thumb, the Q of the filter has to be significantly higher than the maximum expected number N of no-transition bits. As an example, if N=25, Q should be in the range of 500 to 1,000, a very high figure for analog filters.
High-Q high-frequency analog filters are generally complicated and poorly suited for this use, as they suffer the aging and environmental effects common with analog parts. Phase Lock Loops (PLL) are a better choice for such filters, as they are more convenient, economical, flexible, and are self-correcting as to aging effects. However, the operational frequency of a PLL is rather narrowfor rapidly acquiring and efficiently extracting the system clock information, and the continuing evolution of increasing telecommunications speeds could limit the usefulness of a conventional PLL-based CDR or require upgraded capacities.
What is needed is a flexible clock timing and data recovery (CDR) circuit for high speed communications (up through the multiple gigahertz range) which can rapidly detect and maintain clock speeds within a wide range of speeds, from data formats including NRZ data, and that achieves these results at a minimum cost in terms of lost data, functionality, reliability, purchase price and operational expense.